Freescale Semiconductor /MKW20Z4 /I2C0 /FLT

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as FLT

7 43 0 0 00 0 0 0 0 0 0 0 0 (0)FLT0 (0)STARTF 0 (0)SSIE 0 (0)STOPF 0 (0)SHEN

STARTF=0, FLT=0, SSIE=0, STOPF=0, SHEN=0

Description

I2C Programmable Input Glitch Filter Register

Fields

FLT

I2C Programmable Filter Factor

0 (0): No filter/bypass

STARTF

I2C Bus Start Detect Flag

0 (0): No start happens on I2C bus

1 (1): Start detected on I2C bus

SSIE

I2C Bus Stop or Start Interrupt Enable

0 (0): Stop or start detection interrupt is disabled

1 (1): Stop or start detection interrupt is enabled

STOPF

I2C Bus Stop Detect Flag

0 (0): No stop happens on I2C bus

1 (1): Stop detected on I2C bus

SHEN

Stop Hold Enable

0 (0): Stop holdoff is disabled. The MCU’s entry to stop mode is not gated. Clocks to peripherals are gated when the core stop occurs.

1 (1): Stop holdoff is enabled. Stop mode entry is gated until the current transaction phase is complete, and the IP enters stop mode (clocks are gated) after the current phase’s completion. That is to say: If the system stop request occurs between the address or data phase, the stop acknowledge is asserted after the current byte and IIC ack completion (after the acknowledge in the ninth cycle).

Links

() ()